HIvhdl考试时钟实验报告应用技术一班朱晓园，汪仙仙，张明星，胡亚洲一:分频模块定义elk为时钟输入引脚输入20MHZ的频率定义一个clklhz分须和ckllOOHZ分频LIBRARY ieee;USE i eee. std_Iog i c_1164. a 11;USE ieee. std_logic_arith. all;USE i eee. std_Iog i c_uns i gned. all;ENTITY FENPIN ISPORT(elk : IN STD LOGIC；oclk : OUT STD LOGIC;ocIk1OOhz : OUT STD_LOGIC)；END FENPIN;ARCH ITECTURE FENPIN .architecture OF FENPIN ISBEGINprocess(elk)variable ent :integer range 0 to 20000000;beginif rising_edge(cIk) thenent:=cnt+1;if cnt<=10000000 thenoclk<='「；else if cnt<=20000000 thencnt:=0；oelkV'O';end if;end if;end if;end process;process(elk)variable cnt1 :integer range 0 to 20000000;beginif rising_edge(cIk) thenif cnt1<=200000 thencnt1:=0;oclk100hz<='r；elsecnt1 :=cnt1+1;oclk100hz<='0,;end if;end if;end process;END FENPIN architecture;二：按键消抖因为机械键盘存在抖动现象，所以需要用延时，软件去抖。
这里 用100HZ的频率，一旦出现低电平，就计数10次，一共100MS, 然后再次检测，如果仍为低，就输出0信号LIBRARY ieee;USE i eee.std_Iog i c_1164. a I I;USE ieee.std_logic_arith. all;USE ieee. std_ I ogi consigned, all;ENT ITY XIAODOU ISPORT(elk : IN STD LOGIC;rst_key : IN STD_LOGIC;set_key : IN STD_LOGIC;position : IN STD_LOGIC;addup : IN STD_LOGIC;position_s : IN STD_LOGIC;addup_time : IN STD_LOGIC;rst^time : OUT STD_LOGIC;set_t i me : OUT STD_LOGIC);END XIAODOU;ARCH ITECTURE XIAODOU_architecture OF XIAODOU IS s i gnaI cnt:std_logic_vector (3 downto 0);BEGINprocess (elk)beginif rising_edge(cIk) thenif rst_key=,1'thencnt<=n0000n;rst time<=,1';elseif cnt="1001" thenrst time<=,0,;cnt<=cnt;elsecnt<=cnt+1;rst_time<='1';end if;end if;end if;end process;END XIAODOU architecture;三：按键处理信号set键用来检测设置按键，第一次按下，为设置，第二次按下， 为取消按键。
position为位置选择，按下一次选择第一个，按下二次 为第二次，以此类推其余按键正常输出LIBRARY ieee;USE i eee. std_Iog i c_1164. a I I;USE ieee. std_logic_arith. all;USE ieee. std_ I ogi consigned, all;ENT ITY ANJIANCHULI ISPORT(elk : IN STD LOGIC;rst : IN STD LOGIC;set : IN STD LOGIC;add : IN STD LOGIC;position : IN STD_LOGIC;set out : OUT STD LOGIC;rst out : OUT STD LOGIC;add out : OUT STD LOGIC;positionl : OUT STD_LOGIC;position2 : OUT STD.LOGIC;positions : OUT STD_LOGIC;pos i t i on4 : OUT STD_LOGIC)；END ANJIANCHULI;ARCHITECTURE ANJIANCHULI_arch i tecture OF ANJIANCHULI IS signaI ent: std_Iogic_vector(1 downto 0);signaI cnt1: std_Iogic_vector(1 downto 0);beginprocess (set)beginif set'event and set=l0,thencnt<=cnt+1;end if;end process;set_out<='0'when ent (0)=,0'else'1'when ent (0)=,0,else'O';process (position)begin if position'event and position =,0fthen cnt1<=cnt1+1;end if;case cnt1 iswhenn00n=>position1<=,0,;position2<='1 *;position3<=,11;position4<=T;when"01n=>pos i t i on1<='11;pos i t i on2<='0';pos i t i on3<=,1';pos i t i o n4<='1';when"10n=>position1<=,11;position2<=<11;pos i t i on3<='01;positio n4<='1';when"11n=>position1<=,11;position2<='1'；position3<='1';positio n4<=,0,;when others=>nulI;end case;end process;process (elk)beginif rising_edge(cIk)then rst out<=rst: add out<=add:end if;end process;END ANJIANGHULI architecture;四：计数十十进制计数为时钟个位计数，自动计数满10, CY进1给六进制 模块。
手动设置时，不进位LIBRARY ieee;USE ieee. std_Iogic_1164. al I;USE i eee. std_Iog i c_ar i th. a 11;USE ieee. std_Iogic_unsigned. all;ENT ITY JI SHUSH I ISPORT(elk : IN STD LOGIC;rst : IN STD LOGIC;set : IN STD LOGIC;add : IN STD LOGIC;position : IN STD_LOGIC;dataout : OUT STD_LOGIC_VECTOR(3 downto 0)；os : OUT STD LOGIC);END JI SHUSH I vhd;ARCHITECTURE JI SHUSH I_vhd_arch i tecture OF JISHUSHI_vhd IS signaI buffer_os:std_logic;s i gnaI adder_buffer:std_logic_vector(3 downto 0);signaI add_cnt:std_Iogic_vector(3 downto 0);BEGINbuffer_os<='O' when set='0'else elk;process (set, posit ion, buffer_os)beginif rst=,01 thenadder buffer<=n0000"；elsif set='O' and position='O' thenadder_buffer<=add_cnt;elsif rising_edge(buffer_os) thenif adder_buffer=n100111 thenadder buffer<=n0000"；os<='r；elseadder buffer<=adder buffer+1;os<='0';end if;end if;end process;dataout<=adder buffer;process (add)beginif add1 event and add='O' thenif add_cnt=H1OO1n thenadd cnt<="0000n;elseadd cnt<=add cnt+1:end if;end if;end process;END JI SHUSH I vhd architecture;五：计数六六进制计数为时钟个位计数，自动计数满5, CY进1给十进制模块。
手动设置时，不进位LIBRARY ieee;USE ieee.std_Iogic_1164. al I;USE i eee. std_Iog i c_ar i th. a 11;USE ieee. std_ I ogi consigned, all;ENT ITY JISHULIU_vhd ISPORT(elk : IN STD LOGIC;set ： IN STD LOGIC;add : IN STD LOGIC;position : IN STD.LOGIC;rst : IN STD LOGIC;dataout : OUT STD_LOGIC_VECTOR(3 downto 0);os ： OUT STD.LOGIC)；END JISHULIU vhd;ARCHITECTURE JISHULIU_vhd_archi tecture OF JISHULIU_vhd IS signaI buffer_os :std_logic;s i gnaI adder_buffer :std_logic_vector (3 downto 0);s i gnaI add_cnt: std_Iog i c_vector (3 downto 0);BEGINbuffer_os<='0' when set=10,else elk;process(buffer_os, rst, set, position) beginif rst=1O, thenadder buffer<=MOOOOn;elsif set=,O' and position<=*O' then adde r_buffe r<=add_cnt;elsif rising_edge(buffer_os) thenif adder_buffer=,,0101" thenadder buffer<=n0000n;os<='r；elseadder_buffer<=adder_buffer+1;os<=,0";end if;end if;end process;dataout<=adder_buffer;process(add)beginif add 1 event and add='O' thenif add_cnt="0101" thenadd cnt<="0000n;elseadd cnt<=add cnt+1;end if;end if;end process;END JISHULIU vhd architecture;六：译码LIBRARY ieee；USE i eee.std_Iog i c_1164. a I I;USE i eee. std_Iog i c_ar i th. a 11;USE ieee. std_Iogic_unsigned. all;ENT ITY code_moduIe IS—{{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!PORT(data in : IN STD_LOGIC_VECTOR (3 downto 0);dataout : OUT STD_LOGIC_VECT0R(6 downto 0))；END code module:ARCH ITECTURE code moduIe architecture OF code moduIe ISBEGINprocess (data i n)begin case datain is when ,,0000,,=>dataout<="0000001,f；when "0001"=>dataout<="1001111";when n0010"=>dataout<=n0010010";when "0011n=>dataout<="0000110";when "0100n=>dataout<=n1001100"；when n0101n=>dataout<='f0100100n；when “0110” =>dataout<="0100000”；when "0111"=>dataout<="0001111";when n1000n =>dataout<=n0000000"；when ”1001n=>dataout<=H0000100n；when others=>nulI;end case;end process;END code module architecture;七：闪烁当position为0时，让此数码管闪烁，当set和position都为1 时，正常显示。
LIBRARY ieee;USE ieee.std_Iogic_1164. all;USE ieee. std_logic_ar ith. all;USE ieee. std_logic_unsigned. al I;ENTITY FLASH_vhd ISPORT(elk : IN STD_LOGIC;cIk_syn : IN STD_LOGIC;set ： IN STD LOGIC;position : IN STD_LOGIC;data in : IN STD_LOGIC_VECTOR(6 downto 0);dataout : OUT STD_LOGIC_VECTOR(6 downto 0))；END FLASH_vhd;ARCHITECTURE FLASH_vhd .architecture OF FLASH.vhd ISbeginprocess (set, pos i t i on, c I k)beginif rising_edge(cIk_syn) thenif set='O' and position='0' thenif clk=T thendataout<=datain;elsedataout<="1111111,,;end if;elsedataout <= data in;end if;end if;end process;END FLASH vhd architecture; 。